1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a buried bit line, which reduces the space between bit lines, reduces the resistance and also increases the integration of integrated circuits.
2. Description of the Related Art
Memory is widely applied in the integrated circuit industry and plays an especially essential role in the electronic industry. As the industry develops, the demand for high-density memory increases and correlative industries research and develop high density memory to satisfy the demand. Therefore, how to keep the lower resistance of the quality as device dimension is scaled down is now a major problem for the industry to overcome.
For the storage of digital data, the capacitance of the memory is called a "bit" and the unit for data storage in a memory is called a "memory cell". The memory cell is arranged in an array, consisting of columns and rows. A set of a column and a row represents a specific address. Memory cells in the same column or the same row are coupled by a common wiring line, which is called a word line. The vertical wiring line related to data transmittance is called a bit line. Usually, memory is located on chiastic plan of wiring lines that are parallel, buried under bit lines and vertically ranked on the substrate. An obvious case of this is Read-Only Memory (ROM).
FIG. 1 is a top view of a portion (four memory cells) of ROM. FIG. 2 is a cross-sectional view of the ROM shown in FIG. 1.
Referring to FIG. 1, a mask ROM is formed on a P-type substrate 10 and includes buried bit lines 12, 14, 16 which are arranged and formed by selectively doping the substrate 10 to form N-type bit lines. The word lines 18, 20 are arranged in parallel on the substrate 10 surface and perpendicular to the bit lines 12, 14, 16. There is a silicon oxide layer separating the word lines 18, 20.
Mask ROM is a kind of structure having participative bit lines. Bit lines 12, 14, 16 are the source/drain regions of a metal oxide semiconductor field effect transistor (MOSFET), word lines 18, 20 are the gates of MOSFET and the channel region 22, 24, 26, 28 of MOSFET are under the word lines 18, 20 and adjacent to the bit lines 12, 14, 16. However, data storage is achieved by varying transmittance of respective transistors. In other words, data stored in the transistors can be changed by adjusting the threshold voltage of a transistor. Therefore, selecting a different array of transistors with distinct threshold voltage can accomplish ROM programming.
FIG. 2 is a cross-sectional view of the conventional ROM at the dashed line 2-2' in FIG. 1. The conventional method of forming a buried bit line is to cover the substrate 10 with a suitable mask (not shown) and then implant N-type ions into the substrate 10 to form bit lines 12, 14, and 16. As semiconductor integration increases, the cross-sectional area also decreases and therefore electrical resistance rises. The way to solve this problem is to increase the concentration and the depth of the buried bit lines in the substrate. However, as the device dimension is scaled down, it is easy to produce punch through and junction breakage under the normal operative voltages, whether or not the concentration or depth of the buried bit lines in the substrate is increased. The substrate 10, with dopant, is then put into an oxidation environment with high temperature in order to activate impurities in the bit lines and thus an oxide layer is formed on the substrate 10. The oxide layer includes a thinner gate oxide layer 30 located on the channel region 22, 24 and a thicker oxide layer 32 over the bit lines 12, 14, 16. The oxide layer is thicker because the diffusion rate of the heavy doping N-type ions in the bit lines is far higher than the diffusion rate of the light doping P-type ions in the channel 22, 24. But as the gate oxide layer 30 is formed by thermal oxidation, impurities in the buried bit lines are diffused outward under these high temperatures. Therefore, the bit lines cannot be allowed to get too close. The drawback of memory devices with buried bit lines is that the device dimension cannot be scaled down indefinitely. After the oxide layer is completed, a layer of polysilicon, with dopant, is formed to cover the oxide layer 32 and is patterned to form a MOSFET gate electrode 18. The gate electrode 18 serves as a word line of ROM.
As the size of ROM shown in FIG. 1 and FIG. 2 is reduced, the width of buried bit lines 12, 14, 16 becomes smaller and the space between the bit lines is also narrower. The smaller the bit line, the higher the resistance. This reduces the reading and writing speed of ROM. Because the space between bit lines becomes narrower, punch through is more easily produced under normal operative voltages and if punch through occurs, the transistor may be out of control and this constrains the dimension of transistors. Furthermore, impurities in the buried bit lines diffuse outwardly as the gate oxide layer is thermally formed. Thus, it is necessary to fabricate a device structure with reduced dimension which does not affect device performance.